1. Field of the Invention
This invention relates generally to dynamic random access memory (DRAM), and, more particularly, to a two-transistor DRAM cell for logic process technology.
2. Description of the Related Art
The demand for quicker and more powerful personal computers has led to many technological advances in the computer industry, including the development of more efficient dynamic random access memories. However, logic designers continue to strive to improve the memory (bit) density of a chip implemented in logic process technology.
Today, DRAM cells implemented on a chip used in a logic process can be fabricated using DRAM technology or logic process technology. The recent trend in the DRAM technology has been to fabricate a DRAM cell utilizing one transistor coupled to a capacitor. The logic process technology, on the other hand, utilizes three transistors to construct a DRAM cell. The single-transistor DRAM technology offers a higher memory bit density than the three-transistor DRAM of the logic process technology. But, because of performance and economic concerns, it is often desirable to construct the three-transistor dynamic memory using the logic process technology.
The prior art method of implementing a dynamic memory in a logic process requires the use of three transistors. FIGS. 1A and 1B illustrate two possible prior art configurations of a dynamic memory cell 5, 100. The illustration in FIG. 1A differs in one respect from that of FIG. 1B in that the dynamic memory cell 5 depicted in FIG. 1A utilizes a read and write bit line 10, 15 for respective read and write operations, whereas in FIG. 1B the dynamic memory cell 100 utilizes a common read and write bit line 105 for the read as well as the write operation.
The dynamic memory cell 5 of FIG. 1A includes a first, second, and third metal-oxide-semiconductor field-effect transistor (MOSFET) 20, 25, 30, a read and write word line 35, 40, and the read and write bit lines 10, 15. A source terminal of the first transistor 20 is coupled to the write bit line 15, while its gate terminal is coupled to the write word line 40. A drain terminal of the first transistor 20 is coupled to a gate terminal of the second transistor 25. Further, a source terminal of the second transistor 25 is coupled to ground, and its drain terminal is coupled to a source terminal of the third transistor 30. The gate terminal of the third transistor 30 is coupled to the read word line 35 while the drain terminal of the third transistor 30 is coupled to the read bit line 10.
The dynamic memory cell 100 of FIG. 1B includes a first, second, and third metal-oxide-semiconductor field-effect transistor (MOSFET) 110, 115, 120, a read and write word line 125, 130, and the common read and write bit line 105. A source terminal of the first transistor 110 is coupled to the common read and write bit line 105, while its gate terminal is coupled to the write word line 130. A drain terminal of the first transistor 110 is coupled to a gate terminal of the second transistor 115. Further, a source terminal of the second transistor 115 is coupled to ground and its drain terminal is coupled to a source terminal of the third transistor 120. The gate terminal of the third transistor 120 is coupled to the read word line 125 while the drain terminal of the third transistor 120 is coupled to the common read and write bit line 105.
The dynamic memory cells 5, 100 of FIGS. 1A and 1B operate in a similar manner. In both cases, the gates of the second transistors 25, 115 store the charge when the write word lines 40, 130 are activated. The charge is retained due to the inherent capacitance of the gate terminals of the second transistors 25, 115. Once the data is stored in the gate terminals of the second transistors 25, 115, it can be later retrieved by first precharging the read bit lines 10, 105 prior to the read operation and then asserting the read word lines 35, 125. Depending on the charge stored on the gate terminals of the second transistors 25, 115, the read bit lines 10, 105 are either pulled low or kept precharged. The third transistors 30, 120 are used as "amplifiers" to read the stored data from the second transistors 25, 115. The above described operation of the three-transistor dynamic memory cells 5, 100 is well known in the art.
While the above dynamic memory cells 5, 100 having three transistor are capable of storing data, they still suffer from several shortcomings. A three-transistor dynamic memory cell not only has a low memory bit density but also consumes substantial power. Thus, what is needed is smaller dynamic memory cell that consumes less power than the conventional three-transistor dynamic memory cell.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.